As is generally well known in the art, a semiconductor device having a stacked structure of metal-insulator-semiconductor is referred to as a MIS semiconductor device. A transistor which uses an oxide film as the insulator is referred to as Metal Oxide Semiconductor Field Effect Transistor (MOSFET). A typical MOSFET structure includes a pair of source/drain regions (n-type for an N-MOSFET or p-type for a P-MOSFET) formed on a surface of a silicon substrate, a gate oxide film formed on the substrate between the source/drain regions, and a gate electrode formed on the surface of the gate oxide film. The surface area of the substrate between the source region and the drain region is defined as a channel region. The length of the channel region is the distance between the source/drain regions, which is typically somewhat shorter than the gate length.
The threshold voltage V.sub.T for the MOSFET device is defined to be the gate-to-source voltage V.sub.gs applied across the gate and source electrodes, below which the MOS device drain-to-source current I.sub.ds becomes near zero. However, this threshold voltage is a function of a number of parameters, which includes the gate material, the gate insulation material, the gate insulation thickness, the channel doping, the impurities at the silicon-insulator interface, and the source-to-substrate voltage between the source and substrate.
In order to increase the speed of the MOS device, there exists a continuing trend of scaling-down the structure to smaller sizes. One of the ways of scaling is by reducing the length of the gate. However, one of the most pronounced effects occurs due to the gate length reduction is the loss of gate electrode control which is sometimes referred to as threshold (V.sub.T) roll-off. In the classical VLSI circuit design where a very large number of MOSFET devices are fabricated on a plurality of semiconductor integrated circuit dies or chips on a wafer, the distribution of the actual gate length across the wafer will vary due to inescapable process variations. Since the threshold voltage is a function of the gate length, this will also cause the threshold voltages of the various MOS devices on the wafer to be subjected to a wide degree of fluctuation. As a result, the yield for such MOS devices during production will be greatly reduced.
There are known techniques for threshold adjusts which exist in the prior art. For example, in an article entitled "A Novel Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET for High Current Drivability and Threshold Voltage Controllability" and authored by Y. Okumura et al., IEDM 90, pp. 391-394, there is described a method of a MOSFET fabrication where the concentration of the channel near the source and drain is increased to suppress the widening of the depletion region and the concentration in the middle of the channel is decreased so as to increase mobility.
In U.S. Pat. No. 5,466,957 issued on Nov. 14, 1995, to Yuki et al., there is disclosed a semiconductor device which includes a substrate of a first conductivity type, a gate electrode laminated thereon, and source/self-aligned manner in an upper portion of the substrate outside the gate electrode. A high concentration layer of the first conductivity type is formed in a channel region between the source and drain regions. A low conductivity layer of the first conductivity type is formed between the high conductivity layer and the source/drain regions.
There is also known in the prior art a technique for controlling the threshold distribution by threshold adjust implant (channel doping at the silicon-insulation interface) prior to the deposition of the gate polysilicon.
Generally, the prior art techniques for threshold adjust also suffer from the disadvantages of requiring high energy and high-tilt angle implants. Accordingly, there exists a need for a method for forming MOS devices which have a minimal threshold fluctuation across the semiconductor wafer so as to improve its yield, but yet permits the ability to use low energy and low-tilt angle implants.